1. Field of the Invention
The present invention relates to a decoder and a decoding method for executing depacking and variable length decoding of a packed variable length code stream.
2. Description of the Related Art
In a digital video (DV) camera, a moving picture encoder encodes moving picture data so as to record the data on a recording medium, such as a magnetic tape. The encoding process executes a discrete cosine transform (DCT), quantization, and variable length encoding in this order. Since each sampling number of a luminance signal and a chrominance signal in a frame is different, the encoding process is executed for each macro-block including four luminance blocks and two chrominance blocks. With respect to a macro-block, after a variable length encoding, dispersion occurs in the bit length of each of the four luminance blocks in accordance with the complexity of a picture. Similarly, the dispersion of bit length occurs in the two chrominance blocks.
In the magnetic tape tracks for recording variable length encoded moving picture data (hereinafter referred to as “variable length code stream”), each track for recording the variable length code stream is divided into fixed length areas referred to as sync-blocks. Therefore, it is necessary to pack the variable length code stream of a variable length macro-block into a sync-block having a fixed length.
On the other hand, a depacking and variable length decoding are required so as to decode moving picture data from the packed variable length code stream. The packed variable length code stream is stored in a memory, and a variable length decoding is executed. A technique for reducing the capacity of the memory by increasing efficiency of the depacking and the variable length decoding has been proposed. A technique of further increasing efficiency of the depacking and the variable length decoding has also been proposed.
However, in the first and second techniques, it is difficult to improve the operational frequency of entire decoder because a controller in the decoder requires increased complexity. Especially, the circuit scale of the decoder increases because a subtractor having many bits is required for combining the variable length code stream in depacking. Furthermore, a delay time of the decoder increases because of a delay of carry transmission occurs due to the multi-bit subtractor having many bits. Although it is possible to reduce the delay time by utilizing a high performance subtractor, the circuit scale increases. As described above, a decoder capable of achieving both a decrease of the circuit scale and an increase of the operational frequency has been desired.